1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a semiconductor device having recess channel to improve refresh characteristics.
2. Description of the Related Art
With increased integration in semiconductor devices, a process to improve refresh characteristics of capacitors is receiving a great deal of attention. In semiconductor memory devices, for example, volatile memories such as dynamic random access memories (DRAMs), periodic refresh thereof plays a very important role in manufacturing processes of devices. Recently, a great deal of research into the improvement of refresh characteristics has been made, and inter alia, a liner nitride film is utilized as a material for improving refresh characteristics. The liner nitride film serves to prevent passage of an oxygen source through trench isolation films in a subsequent oxidation process for forming a gate insulation film, and is already well known as contributing to the reduction of leakage current, thereby improving refresh characteristics of DRAMs. In addition, in order to improve the refresh characteristics of DRAMs, an approach entailing replacement of a capacitor material with a high-dielectric constant material has been proposed. Exemplary capacitor materials into which a great deal of research has been conducted are hafnium oxide (HfO2) and aluminum oxide (Al2O3). However, as the above-mentioned methods exhibit limitations in improving the refresh characteristics of devices, recent research has been focused on semiconductor devices having recessed channels.
FIG. 1a is an SEM photograph showing a semiconductor device having recessed channels in accordance with a conventional art. FIG. 1b is a drawing equivalent of FIG. 1a, showing the semiconductor device with greater clarity.
Referring to FIG. 1, in the semiconductor device having recessed channels, trenches are formed at a predetermined depth from a surface of a semiconductor substrate 100, gate stacks 112 are disposed on the trenches, and source/drain impurities are implanted to form a channel. The respective gate stacks 112 may be formed including a gate oxide film pattern 104, a conductive film pattern 106, a metal film pattern 108 and a hard mask film pattern 110. Spacer films 114 are disposed on sides of the gate stacks 112. Such a semiconductor device having recessed channels 160 has a relatively long gate channel length as compared to a semiconductor device having plane channels. An increased gate channel length results in elevation of cell threshold voltage, and as a result, an amount of impurities, which are implanted to lower cell threshold voltage to a predetermined level, i.e., boron difluoride (BF2), may be decreased. Decreasing the amount of BF2, which are impurities for control of cell threshold voltage, increases the width of a depletion layer positioned at a source/drain in cell regions, and decreases the amount of electric field, thereby resulting in decreased junction leakage current and gate induced drain leakage (GIDL), and as a result, it is possible to increase the refresh characteristics to about twice those of a semiconductor device having a plane channel.
FIG. 2a is an SEM photograph illustrating problems exhibited in a semiconductor device having recess gates in accordance with the conventional art. FIG. 2c is a drawing equivalent of FIG. 2a, illustrating with greater clarity the location of element 208 and plane X-X′.
FIG. 2b is an SEM photograph showing a cross-section taken along X-X′ direction of FIG. 2a and FIG. 2c. FIG. 2d is a drawing equivalent of FIG. 2b, showing with greater clarity the cross-section taken along X-X′ direction of FIG. 2a and FIG. 2c. 
Referring to FIG. 2a to FIG. 2d, in fabricating a semiconductor device having recess gates, sharp silicon protrusions remained (hereinafter, referred to as “horns”) (as represented by reference numeral 208 in FIG. 2a to FIG. 2d) in the adjoining regions between an active region 200, which is a recess channel region, and isolation regions 202, due to a difference in the etching rate between the semiconductor substrate and isolation films. Occurrence of such horns 208, when electric current passes through gate electrodes, leads to localized electric-field enhancement in the region where horns occurred, thereby severely lowing lowering cell threshold voltage. Herein, details of sidewall oxide films 204 and liner nitride films 206 are omitted in FIG. 2b. Occurrence of horns 208 also sharply increases dependence on back bias. That is, slight changes in back bias result in significant changes in threshold voltage. Further, as a length of a gate channel is increased, resistance thereof is increased and driving current is rapidly decreased.